“開放靈活的平台” T2000——滿足多樣化測試需求的解決(jue) 方案

SoC測試係統T2000產(chan) 品革新是時代進步的標誌。隨著SoC器件的生命周期不斷縮短，芯片製造商以往需要兩(liang) 到三年就購買(mai) 新的測試設備或新一代的產(chan) 品的情況已經改變，有了更具成本優(you) 勢的新選擇。
T2000係統能使客戶用最小的投資，最短的時間來實現新產(chan) 品的量產(chan) 化，並推向市場。
T2000係統是為(wei) 不斷變化的市場需求推出的革新化的解決(jue) 方案。

• Features
• Solution
• Scalability

SoC測試係統T2000Features

While chipmakers enhance the functionality of semiconductor devices and increase multi-functionality, they need to reduce development times. The T2000 is ideal for testing these devices.

Time to Market Reduction - Multi-Session

The T2000 makes it possible to develop device test programs efficiently with minimal investment. With the multi-site CPU architecture unique to the T2000, multiple users can log in to a single test system at the same time, and perform debugging work independently. Up to eight people can work at the same time, contributing to both engineering cost savings and TTM reduction. In addition, eight people can develop separate functions for the same device at the same time, greatly shortening development times.

Best-In-Class Parallel Test Efficiency - Multi-Site Controller

As more DUTs (Devices Under Test) are measured simultaneously, overhead tends to increase, and in general test times tend to be longer. However, the T2000 reduces test time and achieves high throughput with highly efficient multi-site test technology which completely eliminates overhead.

Test Time Reduction - Concurrent Test

The T2000 supports concurrent test functionality which can execute complicated device test in shorter times. Concurrent test can be more easily achieved than in the past, as the T2000 can seamlessly switch between sequential execution and parallel execution of multiple test items. In addition, its concurrent test functionality enables users to rapidly develop test programs with short test times.

Test Cost Reduction

With up to 8,192 digital channels, the T2000 achieves more than twice the parallelism of the previous model, reducing test cost.